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| PRELIMINARY Am79C988A Quad Integrated Ethernet Transceiver (QuIETTM) DISTINCTIVE CHARACTERISTICS s Four independent 10BASE-T transceivers compliant with IEEE 802.3 Section 14 (10BASE-T MAUs) s Direct interface with AMD's Am79C983A IMR2TM repeater device s On-chip filtering -- Eliminates external transmit and receive filters -- Meets IEEE 802.3 (Section 14.3) electrical requirements -- Enables port switching when used with the IMR2 device s Automatic polarity detection and correction s Serial management interface allows transfer of command and status data between the QuIET device and a controller (IMR2 or other device) s Standard Ethernet (Normal) and Full-Duplex modes s Extended distance option to accommodate lines longer than 100 meters s Test functions provided for Loopback, Link Test, Reverse Polarity, and Jabber s 44-pin PLCC CMOS device with a single 5-V supply GENERAL DESCRIPTION The Am79C988A Quad Integrated Ethernet Transceiver (QuIET) device consists of four independent 10BASE-T transceivers which are compliant with the IEEE 802.3 Section 14 (Medium Attachment Unit for 10BASE-T Cabling) standard. When combined with AMD's Integrated Multiport Repeater 2 (IMR2TM) chip, the QuIET device provides a system-level solution to designing a managed 10BASE-T repeater. The QuIET device includes on-chip filtering for both transmit and receive functions, thus eliminating the need for external filters. On-chip filtering meets IEEE 802.3 (Section 14.3) electrical requirements. The QuIET device provides automatic polarity detection and correction and can operate in either normal or fullduplex mode. The QuIET device interfaces directly with the Pseudo AUI (PAUITM) ports on the IMR2 (Am79C983A) device and can also be connected to standard AUI ports. Command and status data are exchanged with the IMR2 device via a serial management interface. Port switching can be easily implemented with the IMR2/QuIET chipset to move individual ports between multiple Ethernet segments under software control. For application examples on building fully-managed repeaters using the QuIET and IMR2 devices, refer to AMD's IMR2 Technical Manual (PID 19898A). The QuIET chip is packaged in a 44-pin plastic leaded chip carrier (PLCC). The device is fabricated in CMOS technology and requires a single 5-V supply. This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 19880 Rev: B Amendment/+2 Issue Date: November 1997 PRELIMINARY BLOCK DIAGRAM QuIET Device PDO[0] PDI[0] PCI[0] PAUI Port Line Drivers and Receivers PDO Squelch Line Driver and Wave-Shaping TXD+ TXD- TXD[0]+ TXD[0]- Line Receiver and RXD+ Smart Squelch RXDPDO[1] PDI[1] PCI[1] PAUI Port Line Drivers and Receivers PDO Squelch Line Driver and Wave-Shaping TXD+ TXD- RXD[0]+ RXD[0]- TXD[1]+ TXD[1]- Line Receiver and RXD+ Smart Squelch RXDPDO[2] PDI[2] PCI[2] PAUI Port Line Drivers and Receivers PDO Squelch RXD[1]+ RXD[1]- Line Driver and Wave-Shaping TXD+ TXD- TXD[2]+ TXD[2]- PDO[3] PDI[3] PCI[3] PAUI Port Line Drivers and Receivers PDO Squelch Line Receiver and RXD+ Smart Squelch RXD- RXD[2]+ RXD[2]- Line Driver and Wave-Shaping TXD+ TXD- TXD[3]+ TXD[3]- Line Receiver and RXD+ Smart Squelch RXD- RXD[3]+ RXD[3]- REXT Internal Bias Reference and Phase-Lock Loop SDATA DIR CLK RST Serial Management Port Control and Status Collision, Loopback, Jabber and Link Test 19880B-1 2 Am79C988A PRELIMINARY RELATED AMD PRODUCTS Part No. Am79C981 Am79C982 Am79C983A Am79C987 Am7990 Am7996 Am79C90 Am79C98 Am79C100 Am79C900 Am79C940 Am79C960 Am79C961 Am79C961A Am79C965 Am79C970 Am79C970A Am79C974 Description Integrated Multiport Repeater+ (IMR+TM) basic Integrated Multiport Repeater (bIMRTM) Integrated Multiport Repeater 2 (IMR2TM) Hardware Implemented Management Information Base (HIMIBTM) Local Area Network Controller for Ethernet (LANCE) IEEE 802.3/Ethernet/Cheapernet Transceiver CMOS Local Area Network Controller for Ethernet (C-LANCE) Twisted Pair Ethernet Transceiver (TPEX) Twisted Pair Ethernet Transceiver Plus (TPEX+) Integrated Local Area Communications Controller (ILACCTM) Media Access Controller for Ethernet (MACETM) PCnetTM-ISA Single-Chip Ethernet Controller (for ISA bus) PCnetTM-ISA+ Single-Chip Ethernet Controller for ISA (with Microsoft(R) Plug n' Play(R) Support) PCnetTM-ISA II Full Duplex Single-Chip Ethernet Controller for ISA PCnetTM-32 Single-Chip 32-Bit Ethernet Controller PCnetTM-PCI Single-Chip Ethernet Controller (for PCI bus) PCnetTM-PCI II Full Duplex Single-Chip Ethernet Controller (for PCI bus) PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems Am79C988A 3 PRELIMINARY CONNECTION DIAGRAM RXD2+ AVDD RXD1+ RXD3+ RXD0+ RXD3- RXD2- RXD1- 6 DVSS 7 8 9 10 11 12 13 14 15 16 17 54 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 DVSS RST REXT TEST DIR CLK SDATA DVDD TXD3+ TXD3AVSS PCI3 PDI3 PDO3 PCI2 PDI2 Am79C988A PDO2 PCI1 PDI1 PDO1 PCI0 18 19 20 21 22 23 24 25 26 27 28 TXD0+ TXD1+ TXD2+ PDI0 PDO0 AVSS TXD0TXD1TXD2AVDD AVDD RXD0- AVSS AVSS 19880B-2 4 Am79C988A PRELIMINARY LOGIC DIAGRAM Ports PAUI TP PAUI TP PAUI TP PAUI TP Serial Interface 19880B-3 LOGIC SYMBOL DVDD Pseudo Attachment Unit Interface (PAUI) Ports (4 Ports) PDO PDI PCI AVDD TXD+ TXDRXD+ RXDTwisted Pair Ports (4 Ports) Am79C988A SDATA DIR CLK RST Serial Management Interface DVSS AVSS 19880B-4 Am79C988A 5 PRELIMINARY ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: Am79C988B J C OPTIONAL PROCESSING Blank = Standard processing TEMPERATURE RANGE C = Commercial (0C to +70C) PACKAGE TYPE J = 44-pin Plastic Leaded chip carrier (PL 044) SPEED OPTION Not applicable DEVICE NUMBER/DESCRIPTION Am79C988B Quad Integrated Ethernet Transceiver (QuIETTM) Valid Combinations Am79C988B JC\T Valid Combinations Valid Combinations table list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. 6 Am79C988A PRELIMINARY PIN DESCRIPTION Analog PDO0-3 Pseudo AUI Data Output Input Single-ended receiver. Data input from the IMR2 device. PDI0-3 Pseudo AUI Data Input Output Single-ended output driver. Data output to the IMR2 device. PCI0-3 Pseudo AUI Collision Input Output Single-ended output driver. Collision output to the IMR2 device. TXD+0-3, TXD-0-3 Transmit Data Output 10BASE-T port differential drivers. RXD+0-3, RXD-0-3 Receive Data Input 10BASE-T port differential receivers. REXT External Resistor Input REXT must be tied to AVDD through a 13 k 1% resistor.This provides the current reference for all internal analog functions. AVDD Analog Power Power Pin These pins supply +5-V power to the analog portion of the device. These pins should be decoupled and kept separate from the digital power plane. AVSS Analog Ground Ground Pin These pins provide the ground reference for the analog portions of the QuIET circuitry. Digital SDATA Serial Data Input/Output Transfers command and status data between the QuIET device and the IMR2 chip. DIR Direction Input Selects the direction of command data and status data transfer between the QuIET device and the IMR2 chip. RST Reset Input, Active Low Resets the internal registers of the QuIET device. CLK Clock Input 20-Mhz clock signal. The clock signal should be the same one that is used by all IMR2 devices connected to the QuIET chip. TEST Input, Active High Reserved for factory use only. This pin does have an internal pull-down, but should be tied LOW for normal operation. DVDD Digital Power Power Pin These pins supply +5-V power to the digital portion of the device. These pins should be decoupled and kept separate from the analog power plane. DVSS Digital Ground Ground Pin These pins provide the ground reference for the digital portions of the QuIET circuitry. Note: All digital I/O pins are CMOS and TTL compatible. Am79C988A 7 PRELIMINARY FUNCTIONAL DESCRIPTION Overview The Am79C988A Quad Integrated Ethernet Transceiver (QuIETTM) device consists of four independent 10BASE-T transceivers which are compliant with the IEEE 802.3 Section 14 (Medium Attachment Unit for 10BASE-T Cabling) standard. The QuIET device includes on-chip filtering for both transmit and receive functions, thus eliminating the need for external filters. It provides automatic polarity detection and correction and can operate in either normal or full-duplex mode. The QuIET device interfaces directly with the Pseudo AUI (PAUITM) ports on the IMR2 (Am79C983A) device. PAUI ports are functionally equivalent to the AUI interface as described in IEEE 802.3 Section 7, but are single-ended and do not have the drive capability specified in the standard. The QuIET device can also be connected to standard AUI ports. Command and status data is exchanged with the IMR2 device via a serial management interface. in IEEE 802.3, Section 14.3.1.3. Proper termination is shown in Figure 2. Each receiver has internal filtering and does not require external filter modules. RXD+ 1:1 100 Twisted Pair 100 RXD- 19880B-6 Figure 2. RXD Termination Receive squelch threshold voltage can be programmed for extended distance mode. In this mode, the differential receive threshold is reduced to allow cable lengths greater than the 100 meters specified in the IEEE 802.3 Standard. Polarity Detection and Reversal The receive function includes the ability to invert the polarity of the signals appearing at the RXD+ pair if the polarity of the received signal is reversed (such as in the case of a wiring error). The polarity detection function is activated following Reset or Link Fail, and will reverse the receive polarity based on both the polarity of any previous Link Test Pulses and the polarity of subsequent packets with a valid End Transmit Delimiter (ETD). When in the Link Fail State, the QuIET device will recognize Link Test Pulses of either positive or negative polarity. Exit from the Link Fail state is caused by the reception of five-to-seven consecutive Link Test Pulses of identical polarity. Both Link Test Pulses and packets are used to determine the initial receive polarity. Once correct polarity is established, the receiver subsequently accepts only Link Test Pulses that are recognized as TRUE rather than inverted. The Link Test pulse follows the template of Figure 14-12 of the IEEE 802.3 10BASE-T standard. Link Test Function The Link Test function is implemented as specified in the IEEE 802.3 10BASE-T standard. A Link Test pulse is transmitted if a port has been idle for a period of more than approximately 16 (+/-8) milliseconds (ms). The QuIET device monitors the 10BASE-T ports for packet and Link Pulse activity. If neither a packet nor a Link Test pulse is received for 79 ms to 102 ms, the port will enter the Link Test Fail State and the QuIET device will inhibit the transmit and receive functions for that port. Link pulses are transmitted when idle conditions are met. When a packet or five-to-seven consecutive Link Test pulses is received, the port exits the Link Fail State and transmit/receive functions are restored. Twisted Pair Transmitters Each TXD port is a differential twisted pair driver. When properly terminated, TXD meets the 10BASE-T transmitter electrical requirements as specified in IEEE 802.3 Section 14.3.1.2. Proper termination, Figure 1, consists of a single 110 ohm +1% resistor across TXD+ and TXDand a 1:1 standard Ethernet transformer. A common mode may be required for EMI considerations. An external capacitor is not required. The load is a twisted pair cable that meets IEEE 802.3, Section 14.4 requirements. The cable is terminated at the other end by a 100 ohm load. The TXD signal is filtered on the chip to reduce harmonic content per IEEE 802.3 Section 14.3.2.1 (10BASE-T). Since filtering is performed by the QuIET device, the TXD signal can be connected directly to a standard transformer. External filter modules are not required. TXD+ 110 TXD- 1:1 Twisted Pair 100 19880B-5 Figure 1. TXD Termination Twisted Pair Receivers Each RXD port is a differential twisted-pair receiver. When properly terminated, RXD ports will meet the electrical requirements for 10BASE-T receivers as specified 8 Am79C988A PRELIMINARY PAUI Ports The PAUI ports are functionally equivalent to AUI ports as described in IEEE 802.3, Section 7. However, they are single ended and, therefore, are not an exact match with the electrical specifications. PDO, PDI, and PCI are functionally similar to DO, DI, and CI, respectively. PDO is the PAUI input from the IMR2 device. This signal is transmitted by the corresponding TXD port. PDI is the data output to the IMR2 device and is the data received by the corresponding RXD port. PDI also loops back data received by PDO to the IMR2 device. PCI is the collision output to the IMR2 device and indicates either a collision on the corresponding port or an excessive continuous data stream on the corresponding PDO. PCI sends a 10-MHz square wave during collision and jabber. Collision Handling Collision is defined for the QuIET device as data being simultaneously transmitted and received at the corresponding TXD and RXD pins. When a collision is detected, the QuIET device sends a 10 MHz signal over the corresponding PCI pin. This is the only action taken by the QuIET device. The generation of the JAM signal is performed by the IMR2 device. Jabber Protection The Jabber function inhibits the twisted pair transmit function of the port if the PDO circuit is active for an excessive period (> 30 ms). If the maximum transmit time is exceeded, the transmitter circuitry is disabled, PDO to PDI loopback is disabled, and a 10 MHz signal is transmitted by PCI. Once the data stream is removed from PDO, 350 ms will elapse before PCI stops transmitting the 10 MHz signal and the TXD circuitry is enabled again. Note that a properly functioning repeater device will never jabber because of the MAU Jabber Lockup Protection (MJLP). Note: The IMR2 device only supports Normal operation. Full-Duplex Mode In Full-Duplex mode a port can transmit and receive simultaneously, and Collision and PAUI Loopback functions are disabled. The normal loopback of PDO to PDI is disabled to allow the RXD signal to be transmitted on PDI. PCI is disabled and Jabber status is only available to the controller through the serial management interface. The serial management interface also transmits Jabber status when the QuIET device is in Normal mode. Serial Management Interface Command and status data are transferred between the QuIET device and the IMR2 device via SDATA. (See Figure 4 for proper interconnections.) The direction of SDATA is set by DIR. All activity on SDATA starts at the edge (rising or falling) of DIR. The DIR pin of the QuIET device connects to DIR[1] of the IMR2 device. The IMR2 device continually cycles DIR[1] LOW and HIGH. LOW is status reporting (SDATA Write) and HIGH is management commands (SDATA Read). The controller (IMR2 device) should keep DIR at one level for the entire bit stream. The status bit stream is described in the Status Reporting section, and the command bit stream is described in the Management Commands section. Each bit on SDATA is held for 2-bit times (200 ns). Status Reporting When DIR switches from HIGH to LOW, the QuIET device drives SDATA with status information (left to right) in the format shown below. After the 29th bit, the SDATA driver turns off. The SDATA driver also turns off if DIR switches HIGH before the 29th bit. Status Information Format 01010A0A1A2A3B0B1B2B3C0C1C2C3D0D1D2D3SSSSSSSS 01010 Preamble QuIET device ID (0000 for QuIET device) 0 Link Fail 1 Link Pass 0 Received Polarity Reversed 1 Received Polarity Correct 0 No Jabber 1 Jabber Not used, logic HIGH Transceiver Modes The QuIET transceivers have two modes of operation: Normal and Full Duplex. In Normal mode, the data flows only in one direction at a time. In Full-Duplex mode, the collision circuitry and the loopback circuitry are disabled. Therefore, transmit and receive can occur simultaneously. The transceiver mode is selected through the serial management interface, which is explained further in the Management Commands and Transceiver Mode Selection sections. Normal Mode The QuIET device defaults to the Normal mode at power up and reset. In this mode, no twisted pair port can transmit and receive data simultaneously. If a port receives data when it is transmitting, the QuIET device sends a collision signal to the IMR2 device via the corresponding PCI pin. An Bn Cn Dn S Preamble The 01010 preamble is an indication to the IMR2 that the transceiver is a QuIET device. QuIET Device ID A0A1A2A3 The QuIET device returns 0000. Am79C988A 9 PRELIMINARY Link Status B0B1B2B3 The QuIET device reports the Link Status of each port. If Link Test is disabled, Link Status indicates a Link Pass. Bn 0 1 Link Fail Link Pass Extended Distance Option E0E1E2E3 This command modifies the RXD circuit of the transceiver to accommodate signal-attenuation lines longer than 100 meters. En 0 Disable Extended Distance Option 1 Enable Extended Distance Option Receive Polarity Status C0C1C2C3 The QuIET device reports the polarity status of each port. Cn 0 1 Reversed Polarity True Polarity F0F1F2F3 Link Test Enable This command enables the corresponding port to perform a Link Test. Link Status will report Link Pass if the Link Test is disabled. Fn 0 1 Disable Link Test Enable Link Test Jabber Condition D0D1D2D3 The QuIET device reports the Jabber Condition status for each port. Jabber is defined as continuous transmissions by a port for more than 30 ms. Dn 0 1 No Jabber Jabber Transmit Link Pulse Enable G0G1G2G3 This command enables the corresponding port to transmit a Link Pulse. The pulse will be transmitted if either a packet or a pulse has not been transmitted for 16 ms. Note that Link Pulses are transmitted when ports are in Link Test Fail. Gn 0 1 Disable Link Pulse Transmit Enable Link Pulse Transmit Management Commands When DIR switches from LOW to HIGH, the QuIET device reads the command sequence over SDATA. Each management command character is held for 2-bit times (200 ns). The command format is as follows. Management Command Format 0E0E1E2E3F0F1F2F3G0G1G2G3H0H1H2H3I J0J1J2J3KSSSSSSS Auto Polarity Correction Enable H0H1H2H3 This command allows the QuIET device to detect and correct the polarity of signals at RXD. Hn 0 1 Enable Auto Polarity Disable Auto Polarity En Fn Gn Hn I Jn Extended Distance Link Test Transmit Link Test Pulses Enable Polarity Correction Loopback Test (All Ports) Transceiver Mode 0 Disabled 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 Enabled 0 Enabled 1 Disabled 0 Enabled 1 Disabled 0 Full Duplex 1 Normal (Default condition - IMR2 only supports Normal) Loopback Test Enable This command enables or disables the loopback test for the twisted pair ports. When enabled, the signal on RXD is retransmitted on TXD. The default condition is loopback test disabled. Note that the TXD drivers have on-chip filtering, which may cause the TXD output to be different from the corresponding RXD input during this test. I 0 1 Enable Loopback Test Disable Loopback Test Transceiver Mode Selection J0J1J2J3 This command sets the QuIET device either in Full-Duplex or Normal mode. The default is Normal mode. Jn 0 1 Full Duplex Normal K S CMOS/PAUI Mode Not used 0 CMOS Mode 1 PAUI Mode Logic HIGH Note: The QuIET device requires DIR to be high for a minimum of 29 data bits (one bit is four MCLKs), which automatically occurs with the IMR2 device. If any other type of controller is used, DIR must still be high at least 29-bit times. After I, SDATA can be all ones. 10 Am79C988A PRELIMINARY CMOS/PAUI Mode Selection This command sets the QuIET interface drivers (PDO, PDI, PCI) to be driven at normal PAUI signal levels or CMOS voltage levels. The default is PAUI levels. Refer to the DC Characteristics table for voltage levels. K 0 1 CMOS Levels PAUI Levels Command and Status Default Conditions Command Extended Distance Link Test Link Pulse Transmit Correct Polarity Loopback Test Transceiver Mode Selection CMOS/PAUI Mode Default Disabled Enabled Enabled Disabled Disabled Normal PAUI Mode Reset Function The QuIET device enters the reset state when the reset pin (RST) is held LOW. All ports, status registers, and command registers are put into their default state. When powering up the device, the RST pin should be held LOW for 150 microseconds (s). At other times, the RST pin should be held LOW for a minimum of 4 s. The default conditions are detailed below. Status Device Link Polarity Jabber Default QuIET Fail Correct No Error Am79C988A 11 PRELIMINARY SYSTEMS APPLICATIONS 10BASE-T Repeaters The IMR2/QuIET chipset provides a system solution to designing 10BASE-T repeaters. Figure 3 shows the necessary connections between the IMR2 device and the QuIET device. Although only one QuIET device is shown for clarity, three QuIET devices are required to build a 12-port 10BASE-T repeater. 10BASE-T ports that can be individually switched between three Ethernet collision domains. The IMR2 and QuIET devices must share a common ground plane and a common power plane. Failure to meet this design requirement may result in false assertion of internal carrier sense or inability to unsquelch in either PDI (for IMR2) or PDO (for QuIET). Connection to Standard AUI Port The PAUI ports on the QuIET device can also be connected to standard AUI ports when used with devices other than the IMR2 chip. Connection to a standard AUI port is not meant to support a full length AUI cable. The AUI connection should remain on the same board as shown in Figure 6. Connection to CMOS Circuits The PAUI ports on the QuIET device can also drive CMOS loads for other devices, including switches. The PDO, PDI, and PCI signals connect directly to the CMOS device. Note that CMOS mode must be selected in the Management Command Frame. Port Switching The IMR2/QuIET chipset supports port switching, which is the ability to move individual ports to any one of multiple Ethernet backplanes under software control. To implement port switching, each port on the QuIET device is connected to two or more IMR2 devices in parallel. Each IMR2 device defines a different logical repeater and constitutes a separate Ethernet collision domain. For each port on the QuIET device, only one corresponding port on the IMR2 devices is enabled at any one time. Figure 4 shows the IMR2 device-to-QuIET device connections necessary for port switching. Note that only one QuIET device is shown for clarity. A full implementation would use three QuIET devices to provide 12 12 Am79C988A PRELIMINARY IMR2 PDO0 PDI0 PCI0 PDO0 PDI0 PCI0 QuIET TXD0+ 110 TXD0RXD0+ RXD0- 100 TP Connector TP Connector TXD1+ PDO1 PDI1 PCI1 PDO1 PDI1 PCI1 TXD1RXD1+ RXD1TXD2+ PDO2 PDI2 PCI2 PDO2 PDI2 PCI2 TXD2110 100 TP Connector 110 RXD2+ 100 RXD2TP Connector TXD3+ TXD3- 110 RXD3+ RXD3100 AVDD PDO3 PDI3 PCI3 PDO3 PDI3 PCI3 MCLK RST RST CLK REXT 13K Typical 19880B-7 Note: Common mode chokes may be required. Figure 3. IMR2 Device to QuIET Device Connection Am79C988A 13 PRELIMINARY QuIET SDATA DIR IMR2 Device SDATA[3] SDATA[2] SDATA[1] SDATA[0] DIR[1] DIR[0] MCLK RST Reset CLK NC NC CLK RST QuIET SDATA DIR CLK RST QuIET SDATA DIR CLK RST Device 2 Device 1 Device 0 19880B-8 Figure 4. IMR2 Device To QuIET Device Serial Interface Backplane 0 PDO PDI PCI PDO PDI PCI PDO PDI PCI PDO PDI PCI PDO PDI PCI PDO PDI PCI SDATA DIR TX A m 7 9 C 9 8 8 RX TX RX TX RX TX RX Port 0 Port 1 Port 2 Port 3 Am79C983 IMR2 0 PDO PDI PCI PDO PDI PCI SDATA[0] DIR[1] Backplane 1 PDO PDI PCI Am79C983 IMR2 1 PDO PDI PCI PDO PDI PCI PDO PDI PCI Backplane 2 PDO PDI PCI Am79C983 IMR2 2 PDO PDI PCI PDO PDI PCI PDO PDI PCI 19880B-9 Figure 5. Port Switching 14 Am79C988A PRELIMINARY 0.1 F 1:1 DO+ 78 DOPDO 12 K 0.1 F 1:1 AUI Port DI+ 200 DI- 10 K PDI 10 K QuIET Device 0.1 F 1:1 CI+ 200 CI- 10 K PCI 10 K 19880B-10 Figure 6. AUI to PAUI Connections Am79C988A 15 PRELIMINARY ABSOLUTE MAXIMUM RATINGS Storage Temperature. . . . . . . . . . . . . -65C to +150C Ambient Temperature Under Bias. . . . . . . . . 0 to 70C Supply Voltage referenced to AVSS or DVSS (AVDD, DVDD) . . . . . . . . . . . . . .-0.3 to +6V Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. OPERATING RANGES Commercial (C) Devices Temperature (TA) . . . . . . . . . . . . . . . . . .0C to + 70 C Supply Voltages (VDD). . . . . . . . . . . . . . . . . +5 V 5% Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over operating ranges unless otherwise specified Parameter Symbol Digital I/O VIL VIH VOL VOH IIH IIL Parameter Description Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage Input Leakage Current HIGH (DIR, SDATA, CLK, RST) Input Leakage Current LOW (DIR, SDATA, CLK, TEST) Input Leakage Current HIGH (TEST) Input Leakage Current LOW (RST) Test Conditions DVSS = 0.0 V IOL=4.0 mA IOH =-0.4 mA 0 Input Leakage Current HIGH Input Leakage Current LOW PDO Squelch (the value PDO must go to before internal PDO carrier sense can be turned on) Twisted Pair Ports IIRXD Input Current at RXD RRXD RXD Differential Input Resistance VTIVB RXD, Open Circuit Input Voltage (Bias) VTIDV Differential Mode Input Voltage Range (RXD) VTSQ+ RXD Positive Squelch Threshold (Peak) VTSQRXD Negative Squelch Threshold (Peak) VTHS+ RXD Post-Squelch Positive Threshold (Peak) VTHSRXD Post-Squelch Negative Threshold (Peak) VDD/2 - 0.400 VDD/2 - 0.175 AVSS 500 AVDD-1.5 3.1 520 -300 293 -120 A k V V mV mV mV mV 16 Am79C988A PRELIMINARY Parameter Symbol VLTSQ+ VLTSQVLTHS+ VLTHSVRXDTH VTXI ITXOFF Parameter Description RXD Positive Squelch Threshold Extended Distance Mode RXD Positive Squelch Threshold Extended Distance Mode RXD Post-Squelch Positive Threshold Extended Distance Mode RXD Post-Squelch Negative Threshold Extended Distance Mode RXD Switching Threshold TXD Differential Output Voltage Imbalance TXD Idle Output Current Test Conditions Sinusoid 5 MHz Max 312 -180 175 -80 +60 +40 2 Unit mV mV mV mV mV mV A DV DD = 5V (Note 2) Power Supply Current IDDTX Power Supply Current (All 4 ports TransF = 20 MHz VDD = VMAX mitting Including TXD current) (Uses Twisted Pair Switching Test Current) IDDI Power Supply Current Idle F= 20 MHz VDD =VMAX - 380 mA - 120 mA Note: 1. CMOS Mode on PAUI signals is guaranteed by design and is compatible with normal CMOS levels present on other QuIET device pins. Am79C988A 17 PRELIMINARY SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified Parameter Symbol Parameter Description Clock and Reset Timing tCLK CLK Clock Period tCLKH CLK Clock High tCLKL CLK Clock Low tCLKR CLK Rise Time tCLKF CLK Fall Time tRST Reset Pulse Width (RST pin LOW) tPRST Reset Pulse Width at Power Up Transmit Timing tPWODO PDO Pulse Width Accept/ Reject Threshold tPWKDO tTON tTSD PDO Pulse Width Maintain/Turn-Off Threshold Test Conditions (Note 1) Min 49.995 20 20 4 150 15 110 250 8 75 20 250 1.0 Max 50.005 30 30 10 10 35 200 300 200 450 24 120 150 750 Unit ns ns ns ns ns s s ns ns ns ns ns ms ns ms ms s (Note 1) (Note 1) Input > VASQ (Max) (Note 3) Input > VASQ (Max) (Note 4) Transmit Start-Up Delay Transmit Static Propagation Delay (PDO to TXD) tTETD Transmit End of Transmission (for TXD) tPERLP Idle Signal Period tPWLP Link Pulse Width tJA Transmit Jabber Activation Time tJR Transmit Jabber Reset Time tJREC Transmit Jabber Recovery Time (Minimum time gap between packets to prevent Jabber activation) tDODION PDO to PDI Start-up Delay tDODISD PDO to PDI Static Propagation Delay Receive Timing tPWORD RXD Pulse Width Accept/Reject Threshold tPWKRD RXD Pulse Width Maintain/Turn-Off Threshold tRON Receiver Start-up Delay (RXD to PDI) tRVD First Validly Timed Bits tRSD Receiver Static Propagation Delay (RXD to PDI) tRETD PDI End of Transmission tRR PDI, PCI Rise Time tRF PDI, PCI Fall Time tRM PDI, PCI Rise and Fall Time Mismatch (tRR - tRF) Collision Timing tCON Collision Turn On Delay tCOFF Collision Turn Off Delay tCPER Collision Period tCPW Collision Output Pulse Width Serial Interface Timing tSDSU CLK to DIR Setup Time tSDHD DIR Hold Time tSSSU CLK to SDATA Setup Time tSSHD CLK to SDATA Hold Time tSSDO CLK to Output Delay (Note 7) (Note 1) (Note 7) (Note 7) (Note 1) (Note 5) (Note 6) 5 136 200 200 - 300 100 35 200 400 tRON +100 70 10 10 5 ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 7) (Note 7) (Note 7) (Note 7) 87 40 10 10 10 10 - 500 500 117 60 40 ns ns ns ns ns ns ns ns ns 18 Am79C988A PRELIMINARY Parameter Symbol tSSDOZ tSDS tDDS Parameter Description Clock to High Impedance Output DIR going HIGH to SDATA Input Valid DIR going LOW to SDATA Output Valid Test Conditions (Note 7) (Note 7) Min -50 100 Max 40 100 150 Unit ns ns ns Notes: 1. Parameter is not tested. 2. Uses switching test load. 3. PDO pulses narrower than tPWODO (min) will be rejected; PDO pulses wider than tPWODO (max) will turn internal PDO carrier sense on. 4. PDO pulses narrower than tPWKDO (min) will maintain internal PDO carrier sense on; PDO pulses longer than tPWKDO (max) will turn internal PDO carrier sense off. 5. RXD pulses narrower than tPWORD (min) will be rejected; RXD pulses longer than tPWORD (max) will turn internal RXD carrier sense on. 6. RXD pulses narrower than tPWKRD (min) will maintain internal RXD carrier sense; RXD pulses longer than tPWKRD (max) will turn internal RXD carrier sense off. 7. Parameter tested functionally. Am79C988A 19 PRELIMINARY KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State KS00010 SWITCHING WAVEFORMS tCLKR tCLKF tCLK tCLKH tCLKL 19880B-11 Figure 7. Clock (CLK) Timing RST tRST tPRST 19880B-12 Figure 8. Reset Pulse 20 Am79C988A PRELIMINARY SWITCHING WAVEFORMS tPWODO PDO tPWKDO tPWKDO tTSD TXD+ tTSD tTON TXD- tTSD tTETD tDODION PDI tDODISD 19880B-13 Figure 9. Transmit Signals tPWORD tPWKRD tPWKRD RXD VTHS+ VTHStRON PDI tRR tRETD tRSD tRF 19880B-14 Figure 10. Receive Signals PDO RXD tCON PCI tCPER tCPW 19880B-15 tCOFF Figure 11. Collision Signals Am79C988A 21 PRELIMINARY SWITCHING WAVEFORMS tPWLP tPERLP 19880B-16 Figure 12. Transmit Link Beat Pulse 50% PDO 0V 0V TXD 50% PCI 0V tJA tJR 19880B-17 Figure 13. Jabber Function 22 Am79C988A PRELIMINARY SWITCHING WAVEFORMS CLK tSDSU DIR SDATA { { { -1 -0 L2 tSDHD tSSHD tSSSU E1 DIR SDATA L3 DIR tSSDO tSSDO SDATA DIR SDATA { M2 M3 19880B-18 Figure 14. Serial Interface Waveforms DIR TSDS (min) TDDS (max) TDDS SDATA 19880B-19 Figure 15. Serial Interface SDATA Transmit and Start Receive Am79C988A 23 PRELIMINARY SWITCHING TEST CIRCUITS VDD R Test Pin 100pF 330* VSS R = 330 for PAUI 1k for SDATA *Not used for SDATA 19880B-20 Test Point Figure 16. Switching Test Circuit TXD+ 110 TXD- TP TP 19880B-21 Figure 17. Twisted Pair Switching Test Circuit 24 Am79C988A PRELIMINARY PHYSICAL DIMENSIONS* PL 044 44-Pin Plastic Leaded Chip Carrier (Measured in inches) .685 .695 .650 .656 .042 .056 .062 .083 Pin 1 I.D. .685 .695 .650 .656 .500 .590 REF .630 .013 .021 .026 .032 .050 REF .009 .015 .090 .120 .165 .180 SEATING PLANE TOP VIEW SIDE VIEW 16-038-SQ PL 044 EC80 11.3.97 lv REVISION SUMMARY This revision (B) reflects changes to Figures 3, 6, and 17. Changes have also been made to the Ordering Information page, and the DC Characteristics and Switching Characteristics tables. No other technical changes have been made. Trademarks Copyright (c) 1997 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof, and QuIET, IMR2, and PAUI are trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Am79C988A 25 |
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